The present invention generally relates to system memory and related components of computer systems. More particularly, this invention relates to a method for altering and preferably optimizing the performance of system memory by tailoring the performance of one or more memory modules to the motherboard of the computer system.
The performance of personal computers depends on the individual components used in its design as well as the interaction between the components. One specific case in point is the system memory. Until the introduction of synchronous DRAM, most memory modules were built according to the best price/performance ratio any manufacturer could define in their specific product. Very often, the deviations from one design to another led to compatibility issues meaning that one computer would only run with a specific module series but not with others, even if the latter were compliant with the general outlines of the specifications.
With the introduction of Synchronous DRAM, Intel Corporation pushed the PC100 and PC66 specifications into the DRAM marketplace, by which a presence indicator was required to enable automatic recognition of a memory module in any given slot. This presence detect feature was incorporated on an Electrically Erasable Programmable Read Only Memory (EEPROM) on the memory module, and interfaced with the motherboard over a dedicated serial bus rather than the parallel command address and data buses used for interfacing between the memory chips on the memory module and the memory controller on the motherboard. This EEPROM is commonly referred to as “Serial Presence Detect” or SPD. In addition to signaling the presence of one or more physical banks, the SPD also contains the entire functional datasheet of the memory module, that is, data corresponding to various physical and operational characteristics of the module, including the number of banks, rows, and columns, and performance parameters such as operating frequency and access latencies, and thermal data relating to specific modes of operation and the presence or absence of heatspreaders. As a result, the SPD is an important factor toward a plug and play implementation of system memory, where any platform-compliant module can be inserted into any open slot and the system will correctly recognize the module and choose the appropriate operating parameters.
The data contained in the SPD are used by the motherboard to configure the mode of operation of the memory controller. That is, the system will boot and run the memory at the frequency specified in the SPD with the latency parameters also specified in the SPD. This aspect of SPDs allows memory manufacturers to program the modules according to their own test criteria and specifications. Recently, there have been extensions to the SPD data that enable platform and user-specific performance modes.
Firmware that contains device-specific data to allow plug and play integration of the device into existing systems is a standard feature of most current computer components. Most motherboards allow upgrading of the firmware or BIOS (basic input-output system) by reprogramming the EEPROM chip onto which the firmware or BIOS is incorporated. Similarly, most graphics cards feature a reprogrammable BIOS, and the same holds for hard disc drives, optical storage drives, network cards, and even integrated peripheral controllers such as RAID controllers. In the latter case, the firmware upgrade is usually an integral part of the motherboard BIOS and will be programmed along with a motherboard BIOS update. Historically, BIOS updates or BIOS flashing has been performed from a DOS prompt or from a utility integrated into the main BIOS that makes the flash utility independent of the operating system used by the computer. Windows® 2000 and XP® also support “Windows®-based” flash utilities, such as Phoenix-Award's Winflash.
BIOS updates have become an important part of personal computing in the enthusiast market, since in many cases it is the end-user feedback that provides the necessary information about bugs in the product that are then fixed in subsequent BIOS revisions. The access of online data bases containing the latest BIOS versions released by any manufacturer allows access and download of the latest binaries. However, such BIOS updates are currently restricted to primarily motherboards, with only a few examples of BIOS updates for other devices such as RAID controllers and graphics adapters being available. In general, BIOS updates work by accessing the EEPROM via a serial bus interface, checking the compatibility of the new BIOS file with the existing hardware based on an ID string, erasing the existing data from the BIOS block and rewriting the binaries to the ROM.
An issue constantly faced by all manufacturers of computer components is that despite the high level of standardization, there is still a substantial fragmentation of the market driven primarily by the need for product differentiation. On the upside, this fragmentation results in optimization; on the downside, however, the result can be compatibility issues or the optimization may not be implemented correctly. Since there are dozens of motherboard manufacturers with several models each, and each motherboard model can go through several firmware or BIOS updates, standardization hits its limitations when it comes to a one-size-fits-all solution regarding memory modules. The result is often finger-pointing between the motherboard and the memory manufacturer and often ends in a compromise that is based on compatibility with other brands in either product category.
A possible solution for this problem would be to allow the motherboard to choose data from a library of SPD entries that is the most suitable for the specific system. In a small scale, this is implemented in the form of frequency versus column address strobe (CAS) latency values stored by the SPD, by which the system can be told to adjust the frequency according to the CAS latency selected. If the system does not power up at the highest frequency, it defaults one step back to the next lower frequency. However, a full implementation of an entire library of SPD data tables featuring all electrical and timing parameters for even the most common boards available at the time of sale far exceeds the capacity of current SPDs. Moreover, SPD content is standardized by the Joint Electron Device Engineering Council (JEDEC) and any change in the overall layout of the SPD data will need to be approved and incorporated into the standard. Therefore, this course of action cannot be considered a solution for the immediate problem of memory optimization.